Apparatus and method for discontinuously operating a receiver

ABSTRACT

An apparatus for discontinuously operating a receiver (302) includes a receive data circuitry (304) and processor circuitry (306). The apparatus and receiver (302) are incorporated in a communication device (104). The receiver (302) receives a communication signal (106) having a plurality of frames (200, 214, 224). Each of the frames has a synchronization field (202, 217, 222) followed by a data field (204, 218, 228). The receive data circuitry (304) synchronizes the communication device (104) with the communication signal (106) received by the receiver (302) according to an initial synchronization field (202). The receive data circuitry (304) decodes the following data field (204). The processor (306) evaluates the decoded data field. If the decoded data field indicates that the receiver (302) is locked, the processor (306) powers off the receiver (302) for the following synchronization fields (222).

FIELD OF THE INVENTION

This invention relates generally to a communication device and, moreparticularly, to an apparatus and method for controlling the operationof a receiver of the communication device.

BACKGROUND OF THE INVENTION

Many communication devices are powered by a battery. Those batterypowered communication devices that minimize power consumption andconserve battery power have a commercial advantage as they help extendthe operating time of the communication device. Accordingly, asignificant amount of money and effort has been expended to reduce theamount of energy consumed by battery powered devices.

Radiotelephones are one type of battery powered communication device.Radiotelephones operate in a communication system by transmitting andreceiving information via channels of the communication system during anactive call state. The radiotelephone employs a receiver capable oftuning to any one of a number of different channels to receiveinformation therefrom. The received information comprisessynchronization fields and data fields. While waiting to place orreceive a call, the radiotelephone monitors the received information ina standby mode. In the standby mode, the radiotelephone remains tuned toone of the channels, and receives and evaluates the synchronizationfields and data fields to determine if it should enter an active callstate.

It is known to periodically power off the receiver during the standbymode to conserve battery power. Schemes for periodically powering offthe receiver are sometimes referred to as "discontinuous receive"schemes. One known discontinuous receive scheme powers off the receiverduring portions of data fields that are predicted to be repetitive.Another known scheme powers off the receiver during data fields that arepredicted to contain data intended for another receiver. However, suchdiscontinuous receive schemes cannot be employed in communicationsystems that require reception and evaluation of each data field in itsentirety.

Therefore, what is needed is an apparatus and method for discontinuouslyoperating a receiver in a communication system that requires receptionand evaluation of data fields in their entirety.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a communication system employingfirst and second communication devices;

FIG. 2 is a diagram illustrating a signaling format for communicatinginformation from the first communication device of FIG. 1 to the secondcommunication device of FIG. 1;

FIG. 3 is a block diagram illustrating apparatus comprising a receivepath of the first or second communication device of FIG. 1; and

FIG. 4 is a flowchart illustrating a method of discontinuously operatinga receiver of the first or second communication device of FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An apparatus for discontinuously operating a receiver includes receivedata circuitry and processor circuitry. The apparatus and receiver areincorporated in a communication device. The receiver receives acommunication signal having a plurality of frames. Each of the frameshas a synchronization field followed by a data field. Thesynchronization circuit synchronizes the communication device with thecommunication signal received by the receiver according to an initialsynchronization field. The decoder decodes the following data field. Theprocessor evaluates the decoded data field. If the decoded data fieldindicates that the receiver is locked in synchronization with thecommunication signal, the processor powers off the receiver for thefollowing synchronization fields.

FIG. 1 illustrates communication system 100. Communication system 100includes communication devices 102 and 104 that communicate overcommunication link 106. Communication devices 102 and 104 can be two-wayradios, cellular radiotelephones, cordless radio telephones, radios,base stations, radio transmitters, personal digital assistants, modems,land line telephones, or the like. The communication link 106 can be awireless connection, a wireline connection such as a twisted wire pair,a coaxial cable, or the like. In the illustrated embodiment,communication system 100 is a cellular radiotelephone system, such as anAMPS (Advanced Mobil Phone Service) system, a NAMPS (Narrow-bandAdvanced Mobil Phone Service) system, a JTACS (Japan Total AccessCommunication Service) system, a NTACS (Narrow-band Total AccessCommunication Service) system, an ETACS (Extended Total AccessCommunication Service) system, a NMT (Nordic Mobile Telephone) system,or the like. The illustrated communication device 102 is a cellular basestation and the illustrated communication device 104 is a cellularradiotelephone compatible with communication device 102. In theillustrated embodiment, communication link 106 comprises an RF (radiofrequency) communication signal consisting of a continuous bit streamsent by communication device 102 and received by communication device104 on any one of a plurality of channels.

A signaling format for information in communication link 106 isillustrated in FIG. 2. The information is a continuous bit streamcomprising a plurality of frames, such as frame 200. Each framecomprises a synchronization field, such as synchronization field 202,followed by a data field, such as data field 204. In the illustratedembodiment, synchronization field 202 further comprises a bitsynchronization subfield, such as bit synchronization subfield 206,followed by a frame synchronization subfield, such as framesynchronization subfield 208. The bit synchronization subfield consistsof a predetermined 15 bit alternating pattern (101010101010101). Theframe synchronization subfield consists of a predetermined 11 bitpattern (11100010010). Also in the illustrated embodiment, the datafield further comprises a mute subfield, such as mute subfield 210,followed by a data subfield, such as data subfield 212. The mutesubfield consists of a 12 bit pattern of alternating parity bits andzeros. The data subfield consists of a 128 bit pattern of alternatingparity bits and data bits. As such, each frame consists of 166 bits.Those skilled in the art will recognize that this specific example of asignaling format is employed in the NMT system, although the inventionmay be advantageously employed in other systems having other signalingformats.

Communication device 104 employs apparatus shown in FIG. 3 to receivethe continuous bit stream sent by communication device 102 viacommunication link 106. Communication device 104 includes antenna 300,receiver 302, receive data circuitry 304, and call processor 306.Antenna 300 couples the continuous bit stream to receiver 302. Receiver302, which can, for example, be a super heterodyne receiver, is tunableto receive the continuous bit stream on any one of the plurality ofchannels. Receiver 302 has a discontinuous mode of operation, that is,receiver 302 is permitted to be powered on by an "ON" signal or poweredoff by an "OFF" signal. The ON/OFF signal is input to receiver 302 viaan ON/OFF port coupled to line 308. Receiver 302 outputs the receivedcontinuous bit stream on line 310 coupled to receive data circuitry 304.

Receive data circuitry 304 includes demodulator 312, data PLL (phaselock loop) 314, data decoder 316, controller 318, data generator 320,bit timer 322. Demodulator 312 is coupled to receiver 302 via line 310to receive the continuous bit stream. Demodulator 312 is implementedusing any suitable means, such as a conventional demodulator employing aknown demodulation technique, such as MSK (Minimum Shift Keying)demodulation. Demodulator 312 serially outputs a demodulated continuousbit stream on line 324.

Data PLL 314 is coupled to demodulator 312 via line 324. Data PLL 314receives the demodulated continuous bit stream output by demodulator 312and detects the demodulated synchronization field thereof. Data PLL 314,responsive to detection, becomes synchronized to the synchronizationfield. Data PLL 314 outputs a clock signal on line 326 via a CLK port ata rate corresponding to the bit rate of the synchronization field of thecontinuous bit stream. Each pulse of the clock signal corresponds to onebit of time in the continuous bit stream. Data PLL 314 outputs thecontinuous bit stream on line 328. Data PLL 314 is permitted to beplaced in a hold mode responsive to a hold signal coupled to a HOLD portof data PLL 314 via line 330. When in the hold mode, data PLL 314 nolonger responds to the continuous bit stream on line 324 and maintainsthe clock signal on line 326 at a constant phase. Data PLL 314 may beimplemented using any suitable commercially available phase lock loop.

Data decoder 316 is directly connected to line 326 and switchablyconnected to line 328 via switch 332. Data decoder 316 operates insynchronization with the clock signal on line 326. Switch 332 isnormally closed to connect line 328 to data decoder 316. Data decoder316 receives the continuous bit stream when switch 332 is connected toline 328. When switch 332 is closed, data decoder 316 monitors thesynchronization field and decodes the data field according to thealternating parity bits contained in the data field and thesynchronization field of the next frame following the data field. Datadecoder 316 stores the data field as it is decoded. Once decoding of thefield is complete, the decoded data field is output on line 334.

Controller 318 is coupled to receive the decoded data field on line 334.Controller 318 can be implemented using any suitable commerciallyavailable microcontroller or microprocessor, such as a 68HC11microprocessor manufactured and sold by Motorola, Inc. Controller 318generates the hold signal on line 330, a switch control signal on line333, a data generation signal on line 336, and a timer set signal online 338. These signals are generated responsive to the decoded datafield received via line 334 and call process control signals receivedvia line 340. Controller 318 outputs the decoded data field to callprocessor 306 on line 340.

Data generator 320 is switchably coupled to data decoder 316 via switch332. Data generator 320 outputs a predetermined number of either logiclow or logic high signals. Data generator 320 may be implemented usingan asynchronous shift register. When the data generation signal isoutput from controller 318 on line 336 to activate data generator 320,switch 332 is controlled via the switch control signal output bycontroller 318 on line 333 to connect data generator 320 to data decoder316. Data generator 320 outputs the predetermined number of all high orall low logic bits which are input into data decoder 316.

Bit timer 322 is coupled to line 326. Bit timer 322 is loaded with apredetermined timer value via a timer load signal on line 338. Thepredetermined timer value corresponds to a predetermined number of bits.Once loaded, bit timer 322 is initiated and decrements for each bit ofthe continuous bit stream by decrementing for each pulse of the clocksignal received via line 326. After decrementing for the predeterminednumber of bits, bit timer 322 expires and outputs a timer expirationsignal via line 338.

Call processor 306 is coupled to receive the decoded data fromcontroller 318 on line 340. Call processor 306 can be implemented usingany suitable commercially available microcontroller or microprocessor,such as a 68HC11 microprocessor manufactured and sold by Motorola, Inc.Call processor 306 evaluates the decoded data field. Responsive to thisevaluation, call processor 306 selectively outputs the ON/OFF signal toreceiver 302. Although shown as separate blocks, one skilled in the artwill recognize that call processor 306 and controller 318 couldalternatively be illustrated as a single controller and implementedusing a single microprocessor such as the aforementioned 68HC11microprocessor.

A method of discontinuous operation of receiver 302 during the standbymode implemented by the apparatus of FIG. 3 is illustrated in FIG. 4.FIG. 4 will be described in conjunction with FIGS. 2 and 3. Thesubroutine is initiated at block 400. The subroutine is performed eachtime communication device 104 tunes to a channel during the standbymode. Call processor 306 generates the ON signal on line 308 to power onreceiver 302 to initiate a scanning mode. During the scanning mode,receiver 302 will scan the channels to look for a valid data channel.The method of FIG. 4 is performed once the valid data channel is found.

At block 402, receiver 302 is tuned to receive the continuous bit streamof communication link 106 on a first channel. As the continuous bitstream is received, it is coupled to demodulator 312 via line 310 fordemodulation. The demodulated data is coupled to data PLL via line 324.

At block 404, data PLL 314 detects the alternating bit pattern of bitsynchronization subfield 206 in frame 200 of the continuous bit stream.Data PLL 314 synchronizes to bit synchronization subfield 206 andgenerates the clock signal on line 326. Data PLL 314 serially couplesthe continuous bit stream to data decoder 316 at block 406.

At block 408, data decoder 316 monitors frame synchronization subfield208 of synchronization field 202. Data decoder 316 compares, in abitwise fashion, frame synchronization subfield 208 to a predeterminedbit sequence stored in data decoder 316. Frame synchronization occurs inframe 200 when synchronization subfield 208 matches the predeterminedbit sequence.

At block 410, data field 204 and, particularly, data subfield 212 isdecoded by data decoder 316. In the illustrated embodiment, datasubfield 212 consists of a 128 bit pattern of alternating parity bitsand data bits. Some of the data bits of data subfield 212 are decodedusing bits in mute subfield 210 and bits in the following frame,indicated in FIG. 2 as frame 214. In particular, the last three databits of data subfield 212 are decoded using the first three zeroes ofbit synchronization subfield 216 of frame 214. As such, data decodingoccurs during synchronization field 217 as indicated by "Data Decode On"for frame 200 in FIG. 2. During data decoding, decoded data bits of datasubfield 212 are stored in data decoder 316. Once decoding of data field204 is complete, the decoded data bits of data subfield 212 are coupledto call processor 306 via controller 318 and lines 334 and 340 at block412.

At blocks 414 and 416, call processor 306 evaluates the decoded databits of data subfield 212 of data field 204. At block 414, callprocessor 306 determines if the decoded data word indicates thatreceiver 302 is locked onto the continuous bit stream, i.e., has framelock. If, for example, the decoded data word is unreadable, frame lockhas not occurred and the method proceeds to block 416 where it is ended.If the decoded data word is valid and indicates, for example, an idleframe, frame lock is deemed to exist and the method proceeds to block418. Once frame lock is established, subsequent synchronization fieldsare not demodulated by demodulator 312 or monitored by data PLL 314.There are sufficient transitions in subsequent data fields to maintainsynchronization of the clock signal with the continuous bit stream.

At block 418, call processor 306 determines if the decoded data bitsindicate that an exit to call processing is required. If, for example,the decoded data bits comprise a page message directing receiver 302 totune to another channel, the method proceeds to block 416 where it isended. If, for example, the decoded data bits comprise data meant foranother receiver, an exit is not required at block 418 and callprocessor 306 signals controller 318 to enable discontinuous operationof receiver 302 during subsequent synchronization fields at block 420.

At block 422, data PLL 314 serially couples data field 218 of frame 214to data decoder 316. At block 424, data decoder 316 decodes apredetermined portion of data field 218. In the illustrated embodiment,at block 424 data decoder 316 decodes and stores up to the end of datafield 218. That is, data decoder 316 decodes all but the last three databits of data subfield 220. As stated, the last three data bits of datasubfield 212 are decoded using the first three zeroes of the followingsynchronization field. Coupling of data field 218 to data decoder 316continues until the end of data field 218 of frame 214 or the beginningof frame 224 in FIG. 2 is reached at block 426.

At block 428 and at the end of data field 218 and the beginning ofsynchronization field 222 of frame 224 of FIG. 2, controller 318 placesdata PLL 314 in the hold mode by generating the hold signal on line 330.At block 430, call processor 306 turns off receiver 302 by generatingthe off signal on line 308. By powering down receiver 302 during thesynchronization fields, overall power consumption during standby issubstantially reduced without losing any data in the data fields. Atblock 432, controller 318 loads bit timer 322 with the predeterminedtimer value and starts bit timer 322. The predetermined value designatesthe amount of time that receiver 302 will remain powered off. In theillustrated embodiment, the predetermined timer value corresponds to theduration of the synchronization field of continuous bit stream ofcommunication link 106, which can, for example, correspond to 26 bits,less 2 bits for proper stabilization after powering receiver 302 backon. As such, the predetermined timer value corresponds to 24 bits.

At block 434 and during synchronization field 222, controller 318generates the data generation signal on line 336 and controls switch 332to connect data generator 320 to data decoder 316. Data generator 320couples the predetermined number of logical bits into data decoder 316.In the illustrated embodiment, the predetermined number of logical bitsis three logical low signals or, more particularly, three logical zeros.Data decoder 316 uses the three logical zeros to decode the remainingportion of data field 218 at block 436. By coupling the requisite numberof zeros into data decoder 316 in this manner, data field 218 can becompletely decoded without receiving bit synchronization subfield 226 orsynchronization field 222 of FIG. 2.

Once data field 218 is completely decoded, it is coupled to callprocessor 306 at block 438. At block 440, call processor 306 evaluatesdata field 218 for frame lock in a manner similar to that used toevaluate data field 204 in block 414. If frame lock does not exist, themethod proceeds to block 416 where it is ended. If frame lock doesexist, the method proceeds to block 442. At block 442, call processor306 evaluates data field 218 for call processing in the same manner thatit evaluated data field 204 in block 418. If an exit to call processingis required, the method proceeds to block 416 where it is ended. If anexit is not required at block 442, the method proceeds to block 444.

Controller 318 waits at block 444 for the timer expiration signalgenerated by bit timer 322 on line 338. In the illustrated embodiment,bit timer 322 will generate the timer expiration signal after 24 bits oftime have elapsed from timer load/start at block 432. Upon reception ofthe timer expiration signal, controller 318 signals call processor 306via line 340. At block 446, call processor 306 generates the on signalon line 308, which in turn causes receiver 302 to power on. At block448, controller 318 terminates the hold signal on line 330 and returnsdata PLL 314 to an active mode of operation. The method then returns toblock 422 where data PLL 314 couples subsequent data fields, such asdata field 228 of frame 224 to data decoder 316.

As described above, once discontinuous operation of receiver 302 hasbeen enabled (beginning at block 420), receiver 302 is powered off forthe duration of the synchronization field (the bit synchronizationsubfield and the frame synchronization subfield) less a stabilizationperiod after powering receiver 302 back on. Such is indicated by"Receiver Off" in FIG. 2. In the illustrated embodiment, receiver 302 ispowered off for approximately 14.5% of the time as determined by thefollowing equation, wherein each bit has an equal corresponding time of1/(bit rate): ##EQU1## The aforementioned method is particularlyadvantageous for use by communication devices that operate incommunication systems employing a communication link that hascomparatively large synchronization fields, such as the NMT system.

Thus, it can be seen that substantial power savings in a communicationdevice can be realized by employing discontinuous operation of areceiver during synchronization fields. The disclosed method does notinterfere with the decoding of any data fields. It is particularlyadvantageous in systems that require decoding of the entire data fieldof each frame and, thus, can not employ prior art methods thatdiscontinuously operate the receiver during reception of the data field.It will be recognized that the aforementioned method and apparatus couldalternatively be used in conjunction with these prior art methods torealize even greater power savings for these systems wherein decoding ofthe data field is not detrimentally affected by the disabling of thereceiver during the data field.

What is claimed is:
 1. A method for discontinuously operating a receiverof a communication device, the receiver for receiving a data stream, thedata stream defined by a plurality of frames, each of the plurality offrames having a synchronization field followed by a data field, themethod comprising the steps of:tuning the receiver to receive the datastream; synchronizing the communication device to the synchronizationfield of a first one of the plurality of frames of the data stream;powering off, once synchronized, the receiver for substantially all ofthe synchronization field of at least one subsequent one of theplurality of frames of the data stream and, thereby, interruptingreceipt of the data stream; generating, in the communication device,predetermined data representative of at least a portion of the datastream; and providing, while the receiver is powered off and the datastream is interrupted, the predetermined data as a substitute for thedata stream.
 2. A method according to claim 1 further comprising thestep of:decoding, while the receiver is powered off, a portion of thedata field of the at least one subsequent one of the plurality of framesusing the predetermined data.
 3. A method according to claim 2 whereinthe step of generating further comprises the substep of:generating, inthe communication device, the predetermined data to be representative ofat least a portion of the synchronization field of the at least onesubsequent one of the plurality of frames.
 4. A method according toclaim 2 whereinthe data stream comprises a continuous stream of bits,and the step of generating further comprises the substep of:generating,in the communication device, the predetermined data to be representativeof a predetermined number of bits of the synchronization field of the atleast one subsequent one of the plurality of frames.
 5. A methodaccording to claim 1 further comprising the step of:decoding, prior topowering off the receiver, the data field of the first one of theplurality of frames using the synchronization field of a second one ofthe plurality of frames, the second one of the plurality of framesfollowing the first one of the plurality of frames and not one of the atleast one subsequent one of the plurality of frames.
 6. A methodaccording to claim 5 further comprising the steps of:evaluating,following decoding of the data field of the first one of the pluralityof frames, the data field of the first one of the plurality of frames;and enabling, responsive to evaluating, powering off of the receiverwhen the data field of the first one of the plurality of framesindicates that the communication device is locked to the data stream. 7.A method according to claim 5wherein the step of generating furthercomprises the substep of:generating, in the communication device, thepredetermined data to be representative of at least a portion of thesynchronization field of the at least one subsequent one of theplurality of frames; and further comprising the step of:decoding thedata field of the second one of the plurality of frames using thepredetermined data.
 8. A method according to claim 7 further comprisingthe steps of:decoding, prior to powering off the receiver, a firstportion of the data field of the second one of the plurality of frames;and decoding, after powering off of the receiver, a second portion ofthe data field of the second one of the plurality of frames using thepredetermined data, the second portion different from the first portion.9. A method according to claim 8 further comprising the steps of:holdingthe data stream at a start of the synchronization field of the at leastone subsequent one of the plurality of frames; loading and starting atimer at the start of the synchronization field of the at least onesubsequent one of the plurality of frames with a predetermined durationsubstantially corresponding to a duration of the synchronization fieldof the at least one subsequent one of the plurality of frames; andremoving holding, upon expiration of the timer, of the data stream priorto a start of the data field of the at least one subsequent one of theplurality of frames.
 10. A method according to claim 8wherein the stepof powering off the receiver further comprises the substep of poweringoff the receiver at a start of the synchronization field of the at leastone subsequent one of the plurality of frames; and further comprisingthe steps of:loading and starting a timer at the start of thesynchronization field of the at least one of the subsequent ones of theplurality of frames with a predetermined duration substantiallycorresponding to a duration of the synchronization field of the at leastone subsequent one of the plurality of frames; and powering on, uponexpiration of the timer, the receiver.
 11. A method for discontinuouslyoperating a receiver of a communication device, the receiver forreceiving a bit data stream, the bit data stream defined by a pluralityof frames, each of the plurality of frames having a synchronizationfield followed by a data field, the method comprising the stepsof:tuning the receiver to receive the bit data stream; synchronizing adata phase-locked loop (PLL) of the communication device to thesynchronization field of a first one of the plurality of frames of thebit data stream; generating a clock signal having a rate correspondingto the bit data stream; coupling the bit data stream to a decoder of thecommunication device; decoding at the decoder the data field of thefirst one of the plurality of frames; evaluating the data field of thefirst one of the plurality of frames and determining that the receiveris locked to the bit data stream; decoding at the decoder a firstportion of the data field of a second one of the plurality of frames;placing the data PLL in a hold mode to interrupt coupling of the bitdata stream to the decoder; powering off the receiver; loading a timerwith a predetermined duration substantially corresponding to a durationof the synchronization field of the plurality of frames; starting thetimer; generating, in the communication device, predetermined datarepresentative of a predetermined number of bits of the synchronizationfield of the plurality of frames of the bit data stream; coupling,during interruption of the bit data stream, the predetermined data tothe decoder; decoding at the decoder a second portion of the data fieldof the second one of the plurality of frames using the predetermineddata; determining expiration of the timer; powering on, upon expirationof the timer, the receiver; and placing, upon expiration of the timer,the data PLL in an active mode to again allow coupling of the bit datastream to the decoder.
 12. An apparatus for discontinuously operating areceiver of a communication device, the receiver for receiving a datastream, the data stream defined by a plurality of frames, each of theplurality of frames having a synchronization field followed by a datafield, the apparatus comprising:receive data circuitry coupled to thereceiver, the receive data circuitry comprising circuitry to synchronizethe communication device to the synchronization field of a first one ofthe plurality of frames of the data stream and supply the received datastream, circuitry to generate predetermined data representative of atleast a portion of the data stream and circuitry to decode the datafield of the plurality of frames upon receipt of the data stream; andprocessor circuitry coupled to the receiver and the receive datacircuitry to evaluate decoded data of the data field of the plurality offrames of the data stream, the processor circuitry, responsive todetermining that the decoded data indicates that the receiver is locked,(1) powering off the receiver during at least one subsequent one of thesynchronization field of the plurality of frames, (2) interruptingsupply of the data stream to the circuitry to decode and (3) couplingthe predetermined data to the circuitry to decode as a substitute forthe interrupted data stream to prevent interruption of decoding of thedata field of the plurality of frames.
 13. An apparatus according toclaim 12 whereinthe circuitry to synchronize and supply of the receivedata circuitry comprises a data phase lock loop (PLL), the data PLL tomonitor the data stream and output a clock signal having a ratecorresponding to the rate of the data stream, the data PLL to output thedata stream to the circuitry to decode, and the data PLL furthercomprises a hold mode, the data PLL, in the hold mode, continuing outputof the clock signal and interrupting output of the data stream.
 14. Anapparatus according to claim 13 wherein the circuitry to synchronize andsupply of the receive data circuitry further comprises a timer coupledto the data PLL to receive the clock signal, the timer beingprogrammable to a predetermined value, the predetermined valueapproximately corresponding to a duration of the synchronization field,the timer, thereafter, decrementing responsive to the clock signal. 15.An apparatus according to claim 13 wherein the circuitry to decode ofthe receive data circuitry comprises a data decoder, the data decoderswitchably coupled to the data PLL to receive the data stream andcoupled to the data PLL to receive the clock signal.
 16. An apparatusfor discontinuously operating a receiver of a communication device, thereceiver for receiving a communication signal, the communication signalhaving a plurality of frames, each of the plurality of frames having asynchronization field followed by a data field, the apparatuscomprising:receive data circuitry coupled to the receiver to synchronizethe communication device according to the synchronization field of afirst one of the plurality of frames, the receive data circuitrycomprising; a decoder switchably coupled to receive and decode the datafield of the plurality of frames, and a data generator switchablycoupled to the decoder, the data generator being operable to shiftpredetermined data into the decoder to permit decoding of the data fieldof the plurality of frames while the receiver is powered off; andprocessor circuitry coupled to the receiver and the receive datacircuitry to evaluate decoded data of the data field of the plurality offrames, the processor circuitry, responsive to determining that thedecoded data indicates that the receiver is locked, powering off thereceiver during subsequent ones of the synchronization field of theplurality of frames.
 17. A radiotelephone comprising:a receiver toreceive a communication signal, the receiver having a discontinuous modeof operation, the communication signal having a plurality of frames,each of the plurality of frames having a synchronization field followedby a data field; a demodulator coupled to the receiver to demodulate thecommunication signal; a data phase lock loop (PLL) coupled to thedemodulator, the data PLL to monitor the synchronization field of thecommunication signal and output a clock signal synchronized therewith,the data PLL to output the communication signal, the data PLL having ahold mode that maintains the clock signal; a decoder switchably coupledto the data PLL to decode the data field of each of the plurality offrames and output a decoded data field therefore; a data generatorswitchably coupled to the decoder and being controllable to shift apredetermined number of predetermined data into the decoder to permitdecoding of a portion of the data field; a timer coupled to the dataPLL, the timer being programmable to a predetermined timer value, thetimer, thereafter, decrementing responsive to the clock signal untilexpiration thereof; and a processor coupled to the receiver, the dataPLL, the data data generator, and the timer, the processor evaluatingthe decoded data field, the processor, responsive to determining thatthe decoded data field indicates that the receiver is locked, placingthe data PLL in the hold mode, powering off the receiver, coupling thepredetermined timer value to the timer, the predetermined timer valuecorresponding to a duration of the synchronization field, controllingthe data generator to shift the predetermined number of predetermineddata into the decoder, powering on the receiver after the expiration ofthe timer, and removing the data PLL from the hold mode.
 18. A methodfor discontinuously operating a receiver of a communication device, thereceiver for receiving a data stream, the data stream defined by aplurality of frames, each of the plurality of frames having asynchronization field followed by a data field, the method comprisingthe steps of:tuning the receiver to receive the data stream;synchronizing the communication device to the synchronization field of afirst one of the plurality of frames; powering off the receiver for thesynchronization field of subsequent ones of the plurality of frames;generating, in the communication device, predetermined datarepresentative of at least a portion of the synchronization field of theplurality of frames of the data stream; and decoding, while the receiveris powered off and receipt of the data stream is interrupted, at least aportion of the data field of one of the plurality of frames using thepredetermined data.
 19. An apparatus for discontinuously operating areceiver of a communication device, the receiver for receiving a datastream, the data stream defined by a plurality of frames, each of theplurality of frames having a synchronization field followed by a datafield, the apparatus comprising:a data phase lock loop (PLL) tosynchronize the communication device to the synchronization field of afirst one of the plurality of frames and to output the received datastream; a data generator to generate predetermined data representativeof at least a portion of the synchronization field of the plurality offrames; a decoder to receive the data stream from the data PLL anddecode the data field of the plurality of frames; and processorcircuitry coupled to the receiver, the data PLL, the data generator, andthe decoder, the processor circuitry, responsive to synchronization ofthe communication device, powering off the receiver during thesynchronization field of subsequent ones of the plurality of frames andconnecting the data generator to the decoder to permit decoding of thedata field of the plurality of frames using the predetermined data whenthe receiver is powered off and the data stream is not being received bythe decoder.